Systematic and automatic testing of integrated circuits (ICs) is becoming increasingly complex as each generation of ICs tends to have a higher component density and increased number of system functionalities than the previous generations. ICs may include numerous functional modules like processors, memory, timers, counters, voltage regulators, etc. The modules may be integrated on a single IC enabling the IC to operate as a standalone system, referred to as a system-on-chip (SOC).
Memory, in particular, forms the largest part of an SOC. The memory may include both read-only memory and read-write memory. Due to dense integration of transistors in the memory, memory particularly, read-only memory (ROM) becomes susceptible to various types of faults, such as stuck-at faults and non stuck-at faults. Examples of non stuck-at faults include, but are not limited to, address decoder delay faults, multiple read faults, and address decoder open faults. Occurrence of any such fault may cause failure of a functionality of the SOC or of the SOC itself. Thus, high complexity and fault sensitivity have made memory testing and diagnosis important.
Testing and diagnosis of a faulty memory helps in identifying the exact location of fault(s) in the memory. Memory testing can be done either externally or internally. External testing offers limited control for embedded memories. For testing the faults internally, test circuits, such as built-in self test (BIST) circuit(s), are fabricated along with the memory.
The BIST circuit generates test patterns and reads contents of the memory in order to test and diagnose the faults present in the memory. This can be done based on a first golden signature. Upon determining a fault, the BIST circuit outputs contents of the memory to a tester for further diagnosis and correction. Such testers have a limited memory and data transfer speed, thus increasing the time taken for debugging the memory.
For detection of address decoder open faults, reading of the contents of the memory cells corresponding to a shifted address and a base address is performed by the BIST circuit. Based on the contents of the memory cells corresponding to the shifted address, a multiple input shift register (MISR) generates a signature, and the signature is used in subsequent comparisons. A comparison of the signature generated by the MISR with a second golden signature yields whether or not the address decoder open faults are present. However, such a scheme may inadvertently cause the contents of the shifted address to be corrupted if the address open decoder faults are present in an address decoder corresponding to the base address.
Moreover, masking of faults or aliasing has also been observed in testing schemes utilizing the MISR. The probability of aliasing is higher for certain algorithms having a complexity O (n, log2n), n being the number of words that have to be tested. Some schemes propose solutions for removal of aliasing and error cancellation through introduction of extra signatures. However, an increased number of signatures results in undue consumption of memory area, silicon area overhead, and increased BIST complexity.